1. Field of Invention
The present invention relates to a manufacturing process for semiconductors. More particularly, the present invention relates to a method for manufacturing a shallow trench isolation (STI) structure.
2. Description of Related Art
A complete integrated circuit is generally made from tens of thousands of transistors. To prevent the short-circuiting of any two neighboring transistors, an insulating layer is normally formed between the transistors for isolating the devices. For example, a shallow trench isolation is formed by etching a trench and then filling the trench with an insulating, material to define an active device area.
FIGS. 1A through 1C are cross-sections showing the progression of manufacturing steps in the production of a conventional shallow trench isolation. First, as shown in FIG. 1A, a substrate 10 is provided. Then, a pad oxide layer 11 is formed over the substrate 10 using a thermal oxidation process. The pad oxide layer can be, for example, a silicon dioxide layer. Thereafter, a silicon nitride layer 12 (Si.sub.3 N.sub.4) is formed over the pad oxide layer 11 using a low pressure chemical vapor deposition (LPCVD) method.
Next, as shown in FIG. 2B, a photoresist layer 13 is formed over the silicon nitride layer 12, and then a photolithographic process is used to form a pattern on the silicon nitride layer 12. Then, the silicon nitride layer 12 is anisotropically etched to expose portions of the pad oxide layer using a dry etching method. Similarly, using a photoresist layer 13 and photolithographic processing again, a pattern is formed on the pad oxide layer 11 and the substrate 10. Then, the exposed pad oxide layer 11 is anisotropically etched by a dry etching method. Etching continues down into the substrate 10, and finally forming a trench 18 having interior surfaces 15 that exposes portions of the substrate 10.
Next, as shown in FIG. 1C, the photoresist layer 13 is removed to expose the silicon nitride layer 12. Then, a liner oxide layer 16 is formed at a high temperature using a thermal oxidation process. The liner oxide layer 16 covers the interior surfaces 15 of the trench 14, and has connection with the pad oxide layer 11 at the top upper corner of the trench 14.
FIG. 2 is a magnified view showing the features at the corner within the dash circle of FIG. 1C. As shown in FIG. 2, a sharp edge near the end of the liner oxide layer is formed at the top upper corner, that is, at the junction between the substrate 10 and the pad oxide layer 11.
Finally, conventional processes are performed to complete the structural formation of a shallow trench isolation. For example, the trench is filled using an insulating material such as silicon dioxide. Other subsequent processes are known to those skilled in the art, therefore a detailed description is omitted here.
In the conventional method, the thickness of both the liner oxide layer and the pad oxide layer is roughly the same. Therefore, due to the over-exposure of the substrate at the upper corner of the trench in a subsequent pad oxide layer removing process, a kink effect is generated at the upper corner location. Hence, besides generating sub-threshold current in the device, a corner parasitic MOSFET will also be formed, leading to substantial current leakage in the device.
Furthermore, in the conventional method, the upper corner is the place where a junction between the substrate and the pad oxide layer is formed. Because the junction is above the upper trench corner, the exposed surface of the substrate is very small. This will lead to the formation of a very thin gate oxide layer in subsequent process. A thin gate oxide layer not only will lower the reliability of the gate, but also will increase the electric field strength at the upper trench corner due to a charge accumulation there. This has the effect of worsening the parasitic device problem even more.
In light of the foregoing, there is a need in the art to improve the structure and manufacturing method of a shallow trench isolation.